|
1
|
|
|
2
|
- Register
- Data cache
- Secondary cache
- Memory
- Disk
|
|
3
|
- More memory packed into an MPP system than a SMP, and cost is less.
- Cache is getting larger – introduction of L2
- 64 bit architecture also give flexibility
|
|
4
|
- integer functional units
- floating point units
- write buffers
- instruction cache
- data cache (primary and secondary)
- stream buffer
- local memory
|
|
5
|
- Do i=1,n
- A(i) = B(i)*n
- Enddo
|
|
6
|
- Processor requests value of B(1) from data cache. Not there, so request
to secondary cache
- Not there either – secondary cache miss. Retrieves a line (8 words, for
L2 cache) from memory; this includes B(1-8)
- L1 receives a line from L2 (4 words), namely B(1-4)
- Processor receives B(1), operates, stores.
- For operation on B(2)-B(4), L1 cache
|
|
7
|
- B(5) requested. Retrieved from L2, B(5-8)
- For operations B(5)-B(8), L1 cache
- B(9) requested. Neither L1 nor L2 has the data, secondary cache miss.
- Request for another 8 word line from memory to L2. System begins to
stream data to cache
- L2 cache puts B(9-16) in another one of its compartments
- 4 line word passed to L1 cache; B(9) operated on, stored
|
|
8
|
- Streaming has begun, so data prefetched. L2 cache anticipates need for
B(17-24) and request is made.
- Requests from L1 for 4word lines for B(1-16), then (17-20), etc
- Complete do loop
|
Notes
