1.Processor requests
value of B(1) from data cache. Not there, so request to
secondary cache
2.Not there either –
secondary cache miss. Retrieves a line (8 words, for L2
cache) from memory; this includes B(1-8)
3.L1 receives a line
from L2 (4 words), namely B(1-4)
4.Processor receives
B(1), operates, stores.
5.For operation on
B(2)-B(4), L1 cache
6.